Fast propagation technique in CMOS integrated circuits
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United States of America Patent
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May 21, 1996
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N/A
app pub date -
Jun 30, 1994
filing date -
Jun 30, 1994
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Abstract
A fast propagation technique for use in CMOS circuits, whereby faster signal transition at an information carrying edge of a propagating signal is achieved at a cost of slower signal transition at the opposite edge. The technique of the present invention skews a size ratio of P-channel pull-up to N-channel pull-down transistors in the CMOS circuit to obtain much faster transition at one (rising or falling) edge of the signal and slower transition at the opposite edge. The fast propagation technique of the present invention is well suited for synchronous digital CMOS circuits such as synchronous RAMs.
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