Apparatus within an integrated circuit for automatically detecting a test mode of operation of the integrated circuit and selecting a test clock signal
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United States of America Patent
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May 14, 1996
Issued Date -
N/A
app pub date -
Jan 26, 1995
filing date -
Nov 3, 1992
priority date (Note) -
Expired
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Abstract
An integrated circuit (IC) includes circuitry for generating a clock signal during both a normal mode of operation and a test mode of operation. During the normal mode, an input clock signal is delayed via a skew corrector. In test mode, an input test clock signal bypasses the skew corrector via a clock signal source selector. The clock signal source selector is controlled automatically by a mode detector that responds to the input clock signals to determine the mode of operation of the IC.
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