Low noise logic family
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United States of America Patent
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May 7, 1996
Grant Date -
N/A
app pub date -
Aug 18, 1994
filing date -
Aug 18, 1994
priority date (Note) -
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Abstract
A low noise logic (LNL) family is disclosed. An inverter 10 has a pair of load devices NL1, NL2 coupled to the drains of NMOS transistors N 1, N2. The input signal is coupled to the gate of N 1. The drain of N 1 is coupled to the gate of N2. A constant current source 12 is coupled between V.sub.ss and the sources of the transistors N1,N2. Trickle current devices NTR1, NTR2 are coupled to the drains of N 1, N2, respectively to insure input control of the output states. A high logic signal on the gate of N1 steers the constant current to the load NL1 and turns NL2 off. A low logic signal on the gate of N1 turns N1 off and applies a high voltage to the gate of N2, turning N2 on. N2 steers the constant current to NL2.
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