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Abstract

A single chip digital signal processor (DSP) includes memory mapped resources and an on-chip direct memory access controller (DMAC). The memory mapped resources of the DSP include an on-chip program memory, an on-chip data memory, internal registers and memory mapped external memories and peripheral devices. The DMAC includes separate address and count registers for handling a primary data transfer and two interrupt data transfers. The count registers share the same decrementer and the address registers share the same address computation circuit. The DMAC also has a dedicated interrupt controller for handling interrupts from a host computer and from peripheral devices. The DMAC processes interrupts from the host and two peripheral devices while a primary direct memory access transfer is being performed by the DMAC without having to store address register and count register information in a memory stacking area. As a result, the DMAC can switch from a primary DMA transfer to an interrupt DMA transfer or a host DMA transfer and back without using any instruction cycles for 'overhead' associated with storing and restoring registers in a memory stacking area. The DMAC also includes a host computer interface that processes host originated data transfer commands for transferring data to and from memory mapped resources of the DSP, and commands for setting the mode of operation of the DSP.

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First Claim