Multilayer antifuse with intermediate spacer layer
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United States of America Patent
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Apr 23, 1996
Grant Date -
N/A
app pub date -
May 27, 1994
filing date -
May 27, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method and structure for an improved antifuse in an integrated circuit having a sacrificial layer under a programming layer which forces a conductive link upon programming to be formed away from corner regions of the via structures. The method includes the unique step of forming an improved aperture or via with sides through an inter dielectric layer where the antifuse is to be located. The improved aperture or via exposes a portion of a metal interconnection line through a portion of sacrificial layer located away from the inter dielectric layer sides. Such improved method of forming the antifuse also provides a superior antifuse structure.
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