Dynamic CMOS logic circuit with precharge
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United States of America Patent
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Apr 16, 1996
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N/A
app pub date -
Sep 14, 1993
filing date -
Sep 14, 1993
priority date (Note) -
Expired
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Abstract
A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function.
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