Data processor in which external sync signal may be selectively inhibited
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United States of America Patent
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Mar 5, 1996
Issued Date -
N/A
app pub date -
Sep 7, 1994
filing date -
Aug 23, 1985
priority date (Note) -
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Abstract
An external sync signal generated by a clock generation circuit inside a single-chip microcomputer is supplied to an external terminal of this chip. The external sync signal is necessary in an external expansion mode but not in a single-chip mode. Therefore, the external sync signal is supplied to the external terminal through a control gate while a suitable control signal is inputted to a control terminal of the control gate. According to this circuit construction, control can be made in such a manner that the external sync signal is not supplied to the output terminal in the single-chip mode. As a result, it becomes possible to prevent noise from entering a signal supplied to an adjacent pin through a coupling capacity between the external terminals in the single-chip mode, and to reduce consumed power of an output buffer circuit which is disposed between the control gate and the external terminals.
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