Importance

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Abstract

A semiconductor memory device according to the invention includes a main memory comprising a number of memory sub-arrays, each coupled to an address and a data bus, for providing or receiving data to an intermediate interface unit. The intermediate interface unit provides data to and receives data from an output bus. Also included in the semiconductor memory device is redundancy circuit including a redundant memory coupled to the output bus for storing a subset of data from one of the sub-arrays in the event that the sub-array is defective. The redundancy circuit additionally includes address fuses for storing the sub-array addresses of the subset of data to be stored in the redundant storage, and compare circuitry coupled to the address bus for comparing the address bus to the stored array addresses to determine if there is a match. In the event of a match, the compare circuitry provides an index to the redundant storage unit and enables it to provide data to or receive data from the output bus, while precluding the intermediate interface from providing data from the main memory array to the output bus.

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First Claim