Shallow trench isolation process for high aspect ratio trenches
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United States of America Patent
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Feb 20, 1996
Grant Date -
N/A
app pub date -
Apr 20, 1994
filing date -
Apr 20, 1994
priority date (Note) -
Expired
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Abstract
Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.
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