Digital phase-locked data recovery circuit
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United States of America Patent
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Feb 13, 1996
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N/A
app pub date -
Nov 14, 1994
filing date -
Jul 6, 1992
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Abstract
A digital phase-locked data recovery circuit having improved noise immunity. The data recovery circuit includes a multi-phase clock for supplying clock signals having a predetermined relative phase relationship. A snap shot sampling network takes samples of an input data signal in response to the multi-phase clock signals. The samples are preferably collected during the duration of boundary sampling windows encompassing transitions in the input data signal. The present invention further includes a network for comparing the received data samples with a sample pattern. A phase encoder then generates error signals in response to the phase comparisons. A phase decoder adjusts the phase of the boundary window in response to the error signal.
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