Logical-to-real address translation based on selective use of first and second TLBs
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United States of America Patent
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Feb 6, 1996
Grant Date -
N/A
app pub date -
Jul 21, 1993
filing date -
Jul 22, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Under such a condition between outputs of AND circuits for outputting All '0' when one of zero detecting circuits of two register identifiers within an instruction register detects '0', instead of a content of a general-purpose register designated by these identifiers, and also a carry derived from a page offset corresponding to an intermediate result of an address adder, when a page address portion of a logical address is known before this logical address is defined, selecting circuits are controlled, and then the address controller is bypassed to retrieve a translation look-aside buffer, thereby defining a real address. In case that the page address portion of the logical address register is identical to the page address portion of the base register, the translation look-aside buffer is previously retrieved in accordance with either the content of the index register, or the content of the base register so that the real address can be defined.
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