Test point reduction system for a printed circuit board test system
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United States of America Patent
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Jan 16, 1996
Issued Date -
N/A
app pub date -
May 14, 1992
filing date -
Oct 30, 1990
priority date (Note) -
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Abstract
A system for reducing the number of points to be tested on a printed circuit board where the printed circuit board includes a plurality of network traces each having end points and a plurality of pads provides for the identification of the end points of each network trace of the plurality of network traces. Certain ones of the plurality of network traces network located within a predetermined distance of one another are grouped to form a plurality of groups of network traces. The identified end points of the grouped network traces are connected together within each group of network traces to form a continuous trace having one pair of end points for each group of network traces. The end points are used for testing the printed circuit board.
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