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Abstract

A master clock generates master clock pulses having a selected frequency. A data clock generates a first data clock pulse corresponding to the leading edge of each master clock pulse and a second data clock pulse corresponding to the trailing edge of each master clock pulse. The first and second data clock pulses are applied to an input node of the data circuit. The data circuit generates a first data signal at an output node in response to the first data clock pulse and a second data signal at the output node in response to the second data clock pulse. There is a selected delay between the time a data clock pulse is applied to the input node and the time a data signal appears at the output node. First and second memory elements are provided for storing the data signals from the data circuit. A signal storing circuit stores the first data signal in one of the first or second memory element in response to the first data clock pulse and stores the second data signal in the other first or second memory element in response to the second data clock pulse. Gating circuitry is coupled to the first and second memory elements and to the master clock for selectively outputting the first and second data signals in accordance with the state of the master clock signal.

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