Column redundancy scheme for DRAM using normal and redundant column decoders programmed with defective array address and defective column address
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 21, 1995
Grant Date -
N/A
app pub date -
Jul 14, 1992
filing date -
Jul 14, 1992
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A random access memory comprising rowlines and columns crossing the rowlines, memory cells being associated with crossings of rowlines and columns; apparatus for connecting the memory cells to columns from voltage carried on the rowlines, the rowlines, columns and memory cells being arranged in more than two adjacent arrays; a column decoder providing access apparatus to columns in all the arrays; apparatus to disable the column access in any or all arrays and apparatus to enable a replacement spare column or columns using a spare column decoder in any or all of the arrays.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully