RAM-logic tile for field programmable gate arrays
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United States of America Patent
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-
Nov 7, 1995
Grant Date -
N/A
app pub date -
Oct 19, 1994
filing date -
Oct 19, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines. Wiring segments run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates and can be efficiently configured into a memory structure and/or logic device.
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