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Abstract

The process for making a matrix of thin layer transistors with memory capacitors includes forming a first conductive layer on a substrate, and in a first mask step, etching it to form row conductors of the matrix, gate contacts of the thin layer transistors and ground electrodes of the memory capacitors; forming a gate-insulating layer for the thin layer transistors; forming a semiconductor layer, especially an a-Si:H semiconductor layer; applying a p- or n-doped semiconductor layer to provide drain and source contacts; forming and etching a second conductive layer for the column conductors of the matrix of the thin layer transistors, the drain and source contacts of the thin layer transistors and the counter electrodes of the memory capacitors in a second mask step; plasma etching of the doped semiconductor layer with the second conductor layer acting as mask and determining an end of the etching process by observing the optical emission of an etching plasma used for the plasma etching; etching the undoped semconductor layer in a third mask step; forming and etching a transparent conductive layer to form an screen element electrode and metallizing the column conductors of the matrix of thin layer transistors to provide conductive connection of their drain contacts with the counter electrodes of the memory capacitors in a fourth mask step; and forming a transparent passivating layer.

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