Timing analysis of VLSI circuits
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United States of America Patent
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Oct 10, 1995
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N/A
app pub date -
Feb 23, 1993
filing date -
Feb 23, 1993
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Abstract
A computer-implemented process for doing timing analysis of a VLSI sequential circuit that includes false paths. It includes the steps of transforming the circuit into a functionally equivalent .delta. path disjoint circuit for a given delay value and propagating all inverters to primary inputs of the circuit and performing a multifault test on all primary input fanouts of a particular length consisting solely either of all zoroes or of all ones.
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