State machine with adaptable timing and state generation mechanisms
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United States of America Patent
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Oct 3, 1995
Issued Date -
N/A
app pub date -
Sep 9, 1992
filing date -
Feb 25, 1992
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Abstract
A state machine in a computer system receives operation parameters, a clock signal and control signals from a control device. The state machine provides output signals in logical output states to perform an operation based on the operation parameters, the clock signal and the control signals. The operation parameters provided by the control device include timing parameters and state parameters which are stored. A counter provides a counter output based on the clock signal and based on the stored timing parameters. A counter control circuit compares the counter output with timing parameters and controls operation of the counter based on the control signals provided by the control device and based on the comparison of the counter output with the timing parameters. A state generator compares the counter output with the state parameters and generates the output signals in logical output states, each logical output state having a duration based on the comparison of the counter output with the state parameters.
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