Apparatus and method for forcing hardware errors via scan
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United States of America Patent
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Sep 19, 1995
Grant Date -
N/A
app pub date -
Dec 18, 1992
filing date -
Dec 18, 1992
priority date (Note) -
Expired
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Abstract
An apparatus and method for forcing stuck-at and transient errors at sequential and combinational logic and signal lines in a large scale data processing system. Error forcing is achieved by including a scan-in gate with error input and address lines for each scan point to be tested. A fault signal of adjustable duration is generated and combined in a unique fashion to an existing scan-in signal to permit either stuck-at or transient errors to be forced.
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