Exploiting multi-cycle false paths in the performance optimization of sequential circuits
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United States of America Patent
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Sep 5, 1995
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N/A
app pub date -
Sep 8, 1992
filing date -
Sep 8, 1992
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Abstract
A methodology for the redesign of sequential VLSI circuits to increase the circuit speed involves cascading the circuit over a plurality of time frames without the memory elements, identifying any long false paths in the cascaded circuit, reconfiguring the original circuit to eliminate the false paths while providing fanout to preserve functionality, and retiming the reconfigured circuit to reduce circuit delay.
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