Importance

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Abstract

An ATM multiplexing system comprising a plurality of ATM cell input circuits, each of which stores a cell stream incoming from a corresponding input stage and absorbs and removes instantaneous displacement of the incoming cells, a priority encoder for receiving simultaneously FIFO storage level information from the ATM cell input circuits and determining a priority for processing first an input stage with the largest number of stored cells, the FIFO storage level information including the number of the cells stored in the ATM cell input circuits, a link table processing circuit for receiving output headers from the priority encoder and input port numbers corresponding to the received headers and outputting changed headers corresponding to the received headers, an ATM cell output circuit for receiving the changed headers and link information from the link table processing circuit, determining a cell transmission order according to a service priority and performing a header assembling function for perfect cell production, a cell transmission controller for transmitting output headers from the ATM cell output circuit and the corresponding payloads and controlling the above-mentioned components, and a clock signal control circuit for generating a clock signal to control timing of the above-mentioned components.

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First Claim