Power on reset signal circuit with clock inhibit and delayed reset
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United States of America Patent
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Aug 29, 1995
Grant Date -
N/A
app pub date -
Feb 4, 1994
filing date -
Feb 4, 1994
priority date (Note) -
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Abstract
A control circuit inhibits the CLOCK input to the CPU during power-up to prevent newer submicron CPUs from locking up during a power-up condition. The control circuit also provides a delayed control signal representing that the power supply has stabilized. This delayed control signal is used to consistently control the RESET signal.
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