Integrated bridge device for optimizing conduction power losses
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United States of America Patent
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Aug 22, 1995
Grant Date -
N/A
app pub date -
Nov 20, 1992
filing date -
Nov 25, 1991
priority date (Note) -
Expired
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Abstract
An integrated bridge device includes at least two arms, each of which is formed of a first and second diode connected transistor in series. The device is formed in an N+ substrate, which forms a positive output terminal. N- and N type epitaxial layers are formed over the substrate, and P and P+ regions are formed therein for each of the aforesaid arms. An N type region is contained within the P and P+ regions, and in turn contains a P type region forming a negative potential output terminal. Also included in the N type region are N++ regions capable of minimizing the current gain of parasitic transistors formed within the device.
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