Importance

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Abstract

A serial input interface circuit includes a shift register connected to a data input terminal, a parallel register coupled via an output buffer to a data bus, a parallel register empty flag and a serial input suspension request flag which can be set, at any time during progress of input processing of input serial data into the shift register even while the parallel register empty flag is reset to indicate absence of parallel data in the parallel register and consequently even while the input serial data are supplied into the shift register, by a program for controlling transfer, to the data bus, of the parallel data which are stored in the parallel register when a predetermined transfer bit length of the input serial data is stored in the shift register. Setting of the serial input suspension request flag sets, in turn, a serial input suspension carry out flag immediately when the parallel register empty flag is reset. This prevents a serial input request signal generating circuit from producing a serial input request signal which would otherwise be produced to continue the input processing when the transfer bit length of the input serial data is stored in the shift register for delivery to the parallel register.

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First Claim