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Abstract

An absolute encoder is comprised of a movable member formed thereon with a plurality of slit patterns to define a plurality of tracks (T.sub.1, T.sub.2) which are bit-coded according to a digital code system such as a binary coded quaternary system indicative of absolute addresses, and which are arranged in parallel manner from a higher order to a lower order. A light source irradiates an illuminating light onto the movable member. A pair of photodetector arrays 1, 2 receive the illuminating light through the slit patterns to output detection signals (A.sub.0.sup.+ -A.sub.3.sup.-) for the respective tracks. A processing circuit processes the detection signals to produce bit signals (P.sub.0 -P.sub.3) and to decode the same to read an absolute address of the movable member. This processing circuit has an operation circuit (3-20) for logically processing lower order detection signals (A.sub.0.sup.+, A.sub.0.sup.-) obtained from the lower order track T.sub.1, with higher order detection signals (A.sub.2.sup.+ -A.sub.3.sup.-) obtained from the higher order track T.sub.2 to produce the higher order bit signals P.sub.2, P.sub.3 in synchronization with either of leading and trailing edges of the lower order bit signal P.sub.0. In order to detect a great number of tracks, the illuminating light from the lower order tracks may be received through an expansion optical system, while the illuminating light from the higher order tracks may be received directly by the corresponding photodetector array.

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