Read and/or write integrated circuit having an operation timing adjusting circuit and constant current elements
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United States of America Patent
Stats
-
Jul 18, 1995
Grant Date -
N/A
app pub date -
Mar 18, 1994
filing date -
Mar 19, 1993
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A timing adjusting circuit is provided to define the operating order of a differential amplifier circuit for amplifying read-out signals and an output circuit in order to minimize changes in output DC level. A damping resistor is disposed between two magnetic head terminals and a clamp circuit in a magnetic head driving circuit. To attend to a composite head configuration, short-circuiting with a power supply and a current flowing into the magnetic head during a non-write operation are detected as abnormalities. In addition, short-circuiting and open-circuiting of the magnetic head are also detected as abnormalities. Also, a read circuit is added to a write magnetic head, in order to output read-out signals in a read mode, so that the read-out signals are utilized for detecting errors in read-out signals from an exclusively designed read head or for detecting and correcting such errors.
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