Test interface for a digital circuit
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United States of America Patent
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Jun 20, 1995
Issued Date -
N/A
app pub date -
Oct 31, 1994
filing date -
Dec 26, 1990
priority date (Note) -
Expired
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Abstract
A test interface is disclosed that is added to a digital circuit device for providing a way of easily verifying that the device's input and output circuits are operating and connected properly. The arrangement implements a test mode in which a simple exercising sequence is placed on any single input of a defined sequential group of device pins. A resultant output can be observed on the next occurring output and all subsequent outputs of the defined sequential group.
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