High voltage negative charge pump with low voltage CMOS transistors
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United States of America Patent
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Jun 6, 1995
Issued Date -
N/A
app pub date -
Apr 26, 1994
filing date -
Jan 5, 1993
priority date (Note) -
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Abstract
A system for erasing a memory array in a memory has a supply voltage and a negative charge pump. The negative charge pump system includes (a) circuitry to select a memory array to be erased; (b) for circuitry to switch on the supply voltage Vnn for the charge pump; (c) circuitry to pump the supply voltage Vnn with the charge pump to produce a pumped negative voltage; (d) circuitry to erase the selected array with the pumped negative voltage; (e) circuitry to provide the pumping; and (f) circuitry to provide a discharge path for voltages trapped in the charge pump.
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