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Abstract

A circuit which synchronizes the phase of a data stream from a transmitting system, to the phase of the clock signal of the receiving system. Two frames of data from the transmitting data stream are stored in a memory which is continuously updated as the data for each time slot is stored in a different word of memory. The storage of the incoming stream data is controlled by the clock signal from the transmitting system. The data stored in the memory is then read out of that memory under control of the clock signal from the receiving system. As each word is read out, it is reinserted into the bit stream that is transmitted to the receiving system. An address control circuit ensures that write addresses have priority over read addresses. Similarly, a read/write control circuit ensures that write signals have priority over read signals. The read signals are arranged such that two read signals are available for each time slot. If there is a conflict between a write signal and the first read signal in a particular time slot, that read signal is inhibited and the second read signal in that time slot will retrieve the data from the memory for insertion in the data stream to be transmitted to the receiving system. If there is no conflict between a write signal and the first read signal, then the first read signal will retrieve the data from memory for insertion in the data stream to be transmitted to the receiving system and the second read signal is inhibited.

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