Interprocessor communication protocol with built-in error prevention encoding
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United States of America Patent
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May 9, 1995
Issued Date -
N/A
app pub date -
Aug 13, 1993
filing date -
May 27, 1992
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A communications protocol for use in a main control processor used in an electronic product, which includes at least a second processor to control the user interface, such as a keyboard and a data display. The protocol gives the main control processor the ability to interpret commands received accurately and to disregard those commands that are erroneous. In addition, the protocol provides the user interface processor with all necessary feedback information it needs to determine its mode of operation or any possible error conditions that may have occurred. Furthermore, the protocol provides each processor the ability to utilize its own resources independently, while at the same time communicating with the coprocessor in a manner that treats the other processors as extended subsets of itself.
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