Memory control device
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United States of America Patent
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May 9, 1995
Grant Date -
N/A
app pub date -
Jul 30, 1992
filing date -
Jul 31, 1991
priority date (Note) -
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Abstract
A memory control device adaptable to various demands and using a standard DRAM. A memory interface for outputting an address of the memory and controllably reading and writing is connected to the memory. A plurality of input and output ports are connected to the memory interface through a local bus. A host interface is connected to the memory interface through the local bus. A refresh control refreshes the memory through the memory interface. An arbitration structure arbitrates the required access to memory between the refresh control means, the input and output ports and the host interface.
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