State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency
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United States of America Patent
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May 2, 1995
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N/A
app pub date -
Feb 25, 1992
filing date -
Feb 25, 1992
priority date (Note) -
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Abstract
A finite state machine has outputs variable between a finite number of logical outputs states. A clock provides a clock signal having clock pulses, with a frequency, to the state machine. A functional circuit determines the logical output states of the state machine based on state inputs to the functional circuit. A variable timer is coupled to the clock and the functional circuit. The variable timer controls the duration of each logical output state to adjust for changes in the clock frequency based on timing parameters provided to the variable timer. The variable timer varies a number of clock pulses corresponding to each logical output state so the duration of each logical output state remains within a predetermined time limit.
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