Two-stage programmable interconnect architecture
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United States of America Patent
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May 2, 1995
Grant Date -
N/A
app pub date -
Apr 14, 1992
filing date -
Apr 14, 1992
priority date (Note) -
Expired
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Abstract
An interconnection matrix configured according to the present invention includes a plurality of conductors disposed on a substrate which may contain an integrated circuit. A first group of the conductors are directly connected to I/O pins provided on the substrate. A second group of the conductors are internal to the substrate. A plurality of programmable elements are disposed on the substrate and are connected between selected ones of the first and second groups of conductors. By selectively programming the antifuse elements, a user may configure the conductors into a custom interconnect pattern. Means are provided to place each conductor in the second group of internal segmented conductors at a selected voltage during programming of the interconnect architecture of the present invention. The antifuses in a selected circuit path between two I/O pads are all initially programmed at an appropriate programming voltage utilizing a low current. After all antifuses in the selected circuit path have been initially programmed, a high programming current is passed through the circuit path between the I/O pads at its ends to complete the programming cycle.
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