Process controller single memory chip shadowing technique
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United States of America Patent
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Apr 25, 1995
Issued Date -
N/A
app pub date -
Jun 13, 1994
filing date -
Apr 20, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A process and apparatus for shadowing memory uses a single memory chip which is addressable into an address field which is smaller than the memory chip. A program having a main control portion is programmed into a main memory area of the memory chip and is directly connected to a main address space of the address field. The program also includes a plurality of secondary program portions which can be used one at a time with the main control portion of the program. Each of the secondary program portions is stored in a separate secondary and shadowed memory area of the memory chip. A secondary address space of the address field which is large enough to accommodate only one secondary memory area at a time, is controlled so as to be latched to only one secondary memory area at a time. Latching is achieved through higher bits of address locations in a selected portion of the address field. Interrupt and power-up routines are provided in the main portion of the program to avoid entering and leaving the program through different secondary program portions.
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