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Abstract

An oscillator system and method in which a time period (inverse of frequency) of a multi-stage ring oscillator (ROSC) is adjusted by a bias current which controls the charging and discharging times of respective capacitors (e.g., interelectrode capacities) within each stage. The time periods of the unadjusted oscillator are counted along with the time periods of a reference clock over a same period of time and a count difference between the two counts is determined. The count difference is applied by a logic circuit in accordance with an algorithm relating count differences to incremental bias current levels to adjust the frequency of the oscillator. The logic circuit generates digital gate signals corresponding to the count difference and these signals automatically select the bias current level needed to bring the oscillator frequency into close agreement with the reference clock frequency. The digital gate signals are stored in a non-volatile memory so that the oscillator will continue to operate at the adjusted frequency (i.e., that of the reference clock) even if the reference clock is no longer present and power is temporarily removed. The oscillator system is well suited for implementation by complementary metal oxide semiconductor (CMOS) technology as part of an integrated circuit (IC).

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