Cell delay addition circuit
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United States of America Patent
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Feb 28, 1995
Grant Date -
N/A
app pub date -
Jul 2, 1993
filing date -
Jul 10, 1992
priority date (Note) -
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Abstract
A cell delay addition circuit can easily feed any desired delay to each of input cells in a communication apparatus or the like for asynchronous transfer mode operation. A time stamp is obtained for an inputted cell based on a sum of a delay amount from a delay amount producing circuit and the current time produced by a clock circuit. The time stamp and the input cell are written in a cell buffer. On the reading side, a comparator reads out a time stamp from the cell buffer and when the comparator detects that the current time tm is equal to or greater than the time stamp, the comparator produces a cell output enable signal ce so that the cell buffer produces the cell.
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