DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
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United States of America Patent
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Jan 10, 1995
Grant Date -
N/A
app pub date -
Oct 15, 1991
filing date -
Oct 15, 1991
priority date (Note) -
Expired
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Abstract
A direct memory access (DMA) controller for exchanging data information between a system memory and an input/output (I/O) device in an initial data exchange mode and an alternate data exchange mode includes a register for exchanging the data information during both modes and a residual data register for storing residual data information in the register upon commencement of the alternate data exchange mode and for providing the residual data information when the initial data exchange mode is restarted.
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