Importance

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Abstract

A clock control circuit 84 is provided which includes circuitry 98 for selecting a master clock from among at least two input clocks provided to clock control circuit 94, the selection made in response to master clock selection control signals. Circuitry 104 is coupled to circuitry for selecting 98 for providing at least first and second divided down clocks each being of a different divide ratio of the master clock. Circuitry 108 is coupled to circuitry for providing divided down clocks 104 for selecting an output clock from between at least the first and second divided down clocks in response to output clock selection control signals received by clock control circuit 84. Circuitry 120 is provided coupled to circuitry for selecting an output clock 108 for selectively controlling the output of the output clock, circuitry for controlling output clock 120 enabling output of the output clock in response to a first output clock control signal received by clock control circuitry 84 and disabling output of the output clock in response to a second output clock output control signal received by clock control circuit 84. Circuitry 120 is further operable to selectively output an additional output clock cycle in response to a control signal during a period when circuitry for controlling 120 has disabled output of the output clock.

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First Claim