Process for producing non-volatile memory devices having closely spaced buried bit lines and non-overlapping code implant areas
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United States of America Patent
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Jan 3, 1995
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N/A
app pub date -
Apr 8, 1994
filing date -
Apr 8, 1994
priority date (Note) -
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Abstract
This inventions provides a method to form metal lines with smaller line pitches than is possible using the conventional photolithographic single coating process. This invention provides for a double photolithographic process where the surface is coated, exposed and developed twice to form two sets of resist patterns. These resist patterns are used to form metal lines over all the buried bit lines. These metal lines provide better masking of the bit lines from the code implants thereby reducing bit line resistance and increasing ROM read speed.
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