Method for controlling the etching profile of a layer of an integrated circuit
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United States of America Patent
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Jan 3, 1995
Grant Date -
N/A
app pub date -
Aug 5, 1992
filing date -
Aug 5, 1991
priority date (Note) -
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Abstract
The invention concerns a process for slope etching a layer of an integrated circuit. The layer to be etched is coated with a masking photoresist layer. The process consists of jointly performing a passivation of the etching flank of the layer to be etched and a nonisotropic erosion of the masking photoresist layer, which makes it possible to control the slope of the etching flank of the layer to be etched.
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