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Abstract

A fault tolerant clock system that includes voting of power-on and other reset signals to ensure tight synchronization. A fault tolerant clock system (10) includes four channels, providing tolerance to a catastrophic failure in one of the channels and a second fault in another channel. Each clock channel comprises a crystal oscillator (12), an RC circuit (14), and a gain circuit (16) that are connected in a feedback loop with a first voter module (18). The first voter module produces a voted time base output signal corresponding to a majority vote of the timing signals provided by each of the four clock channels. This voted time base signal is fed back to the crystal oscillator through the RC circuit. The RC circuit enhances the frequency pulling capability of the crystal oscillator, enabling its timing signal to be phase shifted over a relatively wide range so that it can be kept in phase and frequency synchronization with the timing signals from crystal oscillators in the other clock channels without need for critically trimming components. A second voter module (34) determines a majority vote of reset signals from each of the clock channels, and the voted reset signal is applied to an enable circuit (24) to reset the fault tolerant clock system. A power-on reset circuit (28) controls the duration of reset signal in each channel following a reset caused by application of power to the clock channel or due to manual or other resets, thereby providing sufficient time to enable the power supply and crystal oscillator to stabilize before the time base output signal of the clock channels is again enabled. The enable signal is processed through an optional deglitching circuit 22, which masks out possible glitches on the reset line. Preferably, the fault tolerant clock system is produced on an ASIC to achieve redundancy at the chip level.

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First Claim