Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements
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United States of America Patent
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Dec 6, 1994
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N/A
app pub date -
Mar 29, 1993
filing date -
Sep 3, 1991
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Abstract
A programmable logic device is provided that has a two-dimensional array of logic array blocks. The logic array blocks, which contain advanced macrocells, contain programmable input arrays based on pterm logic and are two-dimensionally interconnected with global horizontal and vertical conductors. The logic array blocks and the connections between conductors are configured using programmable multiplexers and demultiplexers. Redundant conductive pathways are provided so that the programmable logic device may be efficiently programmed to perform a variety of logic functions. Furthermore, logic is provided with each logic array block that allows the global horizontal and vertical conductors to be interconnected without directly involving the logic in the logic array block, which therefore can be used to provide greater logical functionality.
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