Method for constructing a reduced capacitance chip carrier
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United States of America Patent
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Nov 29, 1994
Issued Date -
N/A
app pub date -
Apr 8, 1992
filing date -
Dec 8, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method for making an integrated circuit chip carrier having reduced and regulable interlead capacitance and reduced glass chip formation. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.
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