CMOS/ECL level converting circuit
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United States of America Patent
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-
Oct 4, 1994
Grant Date -
N/A
app pub date -
May 10, 1993
filing date -
May 12, 1992
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A bipolar transistor, connected between a high voltage source and a low voltage source, has a base connected to an input terminal. A clamp circuit is connected between the high voltage source and the base of the transistor. A first resistor is connected in parallel with the clamp circuit. An output terminal is connected to the emitter of the bipolar transistor. In one embodiment, the clamp circuit is formed by two diodes connected in series. In another embodiment, a second resistor for limiting current is provided between the input terminal and the base of the transistor. In yet another embodiment, the resistance value of the first resistor is smaller than the ON resistance of a pMOS transistor in the output circuit of a CMOS circuit connected to the input terminal. A high level from the output terminal produces a high level ECL level output with a potential that depends on V.sub.BE of the bipolar transistor, while a low level output depends on the level of the clamp circuit. High speed operation is obtained without fluctuation of the duty ratio and reduction of high potential level of the output signal from the output terminal.
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