Shift register system for driving active matrix display
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United States of America Patent
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-
Aug 2, 1994
Grant Date -
N/A
app pub date -
Apr 27, 1993
filing date -
Apr 27, 1993
priority date (Note) -
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status (Latency Note)
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Abstract
A clock control circuit for sequentially enabling the clock input terminal of a number of groups of shift register stages for reducing the power consumption. The groups are seccessively activated, and the groups currently not in operation are made not to consume power. During changeover between adjacent groups of shift register stages, the clocks for the different groups overlap to insure stable operation.
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