Protective circuit for protecting contacts of monolithic integrated circuits by preventing parasitic latch up with other integrated circuit elements
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United States of America Patent
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Jul 5, 1994
Grant Date -
N/A
app pub date -
Oct 2, 1992
filing date -
Oct 22, 1991
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A protective circuit for connecting contacts of monolithic integrated circuits, particularly CMOS input/output stages. The protective circuit has a four-layer device (ta, ts) with a defined switching threshold in the area of each connecting contact (A) and a low-resistivity current path (sa) from the connecting contact (A) to a supply terminal (VSS, VDD). The protective circuit also contains devices (zw2, z5) which prevent or provide a bypass for any undesired flow of current (i3, i4) between at least parts of the four-layer device and triggerable circuit regions (W2).
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