Method for forming a dual thickness dielectric floating gate memory cell
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United States of America Patent
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Jun 28, 1994
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app pub date -
Jun 18, 1992
filing date -
Jun 21, 1989
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Abstract
A semiconductor integrated circuit device is disclosed having first and second conducting layers, with the first layer having a shape which enhances field emission tunneling off of the surface thereof. A dual thickness dielectric layer separates the conducting layers. When a potential difference is applied between the conducting layers, field emission tunneling occurs primarily through the thinner portion of the dielectric layer. A method for forming a semiconductor integrated circuit device comprises the steps of (a) forming a first conducting layer, (b) forming regions of enhanced field emission on said first conducting layer, (c) forming a second insulating layer on the first conducting layer, (d) forming a masking layer (e) undercutting the second insulating layer, (f) etching the first conducting layer according to the masking pattern, (g) forming a third insulating layer on all exposed surfaces of the first conducting layer, such that a resultant insulating layer has first and second regions of different thicknesses, and (h) forming a second conducting layer over said resultant insulating layer.
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