Process for fabricating an integrated circuit device by forming a planarized polysilazane layer and oxidizing to form oxide layer

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United States of America Patent

PATENT NO 5310720
SERIAL NO

08021573

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A thick planarization layer of silicon dioxide that is heat resistant is provided by coating a polysilazane layer over a substrate having steps and firing the polysilazane layer in an oxygen-containing atmosphere to convert the polysilazane to silicon dioxide. The temperature of this conversion may be as low as 400.degree. to 450.degree. C. while a higher firing or curing temperature is preferable to obtain a more densified oxide layer.

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Patent Owner(s)

Patent OwnerAddress
FUJITSU SEMICONDUCTOR LTDKANAGAWA COUNTY YOKOHAMA JAPAN

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Harada, Hideki Kagoshima, JP 73 658
Shin, Daitei Kawasaki, JP 5 129

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