Wafer scale or full wafer memory system, packaging method thereof, and wafer processing method employed therein
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United States of America Patent
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May 3, 1994
Issued Date -
N/A
app pub date -
Oct 14, 1992
filing date -
Apr 22, 1987
priority date (Note) -
Expired
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Abstract
To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.
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