Alignment check pattern for multi-level interconnection

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United States of America Patent

PATENT NO 5308682
SERIAL NO

07955027

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An alignment check pattern formed by a first insulating film; a first dummy pattern formed on a surface of said first insulating film; a second insulating film formed on a composite surface of said first insulating film and said first dummy pattern; a second dummy pattern formed on said second film, and positioned directly over said first dummy pattern in plan view; a third insulating film formed on a composite surface of said second insulating film and said second dummy pattern; a regular scale pattern formed on said third insulating film, and positioned directly over said second dummy pattern; fourth insulating film formed on a composite surface of said third insulating film and said regular scale pattern; and a vernier scale pattern formed on a surface of said fourth insulating film and positioned directly over said regular scale pattern.

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Patent Owner(s)

Patent OwnerAddress
NEC ELECTRONICS CORPORATIONKAWASAKI KANAGAWA 211-8668

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Morikawa, Takenori Tokyo, JP 14 294

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